library verilog;
use verilog.vl_types.all;
entity \BUFFER\ is
    port(
        control_input   : in     vl_logic;
        data_input      : in     vl_logic_vector(3 downto 0);
        data_output     : out    vl_logic_vector(3 downto 0)
    );
end \BUFFER\;
